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How can I know what my synthesis tool (XST) is doing with my design? My problem is I can monitor only top level ports of my design after synthesis.So all I can tell is, my design is not working after synthesis :(I'm not aware of any 'standard way' to debug a post synthesis netlist other than to put on your engineer hat and start trying to work backward through the design to see where it's going wrong.Don't know about the specifics of your tool, but perhaps theres a way you can add keep nets to key signals in your design and see if they are behaving properly. Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5). However, things are chaotic when the FPGA starts up, because: So the initial Flip-Flop values after the GSR are not enough.You say that you can only see the top level ports, is there a reason why you cannot run the simulation against your synthesis netlist and dump the full waveform? Create a module that generates a reset signal for each clock domain.Dmitry Grigoryev took care of it already, but there are a few things I want to add, and since I can't comment...

It turns out that XST has two different VHDL parsers, the newer one seems to be better.Interestingly when I design a test bench around the functions the results are correct.When I simulate my design in the project using a combination of generates and functions the hardware is wired correctly.Functions works, at this stage maybe 2% of the available resources have been used. The only genuine wrong-hardware bug I have seen in XST has to do with signals passed as OUT parameters to procedures within a process...Are there any secret flags or peculiarities anyone knows of? the signals were assigned using variable assignment (immediate assignment) semantics!

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